The present invention relates to sampling Automated Test Equipment ("ATE") for testing digital integrated circuits.
The demand for ever-higher performance in computers, workstations, and consumer products is ongoing. With this evolution comes the need for chips with ever-higher frequencies of operation and pin counts. (As of 1997, chips with hundreds of pins may operate at clock speeds of hundreds of Megahertz, i.e. hundreds of millions of cycles per second.) This makes testing very difficult. Among high speed RISC chips, the latest generation microprocessors, and the higher-end application specific integrated circuits ("ASICs"), there are examples of integrated circuits having a complex functionality and very high speed requirements. As design, simulation, and fabrication methods for digital integrated circuits continuously improve, today's integrated circuit designers and test engineers are becoming increasingly concerned about accuracy, validity, and reliability of the tests used to evaluate the prototype devices. Assuring that the specified performance (with respect to both waveforms and timing edges) is present in these integrated circuits requires an ATE system having matching performance.
Background: Conventional Testers
A major component of ATE systems is pattern memory subsystems. In conventional ATE testers (FIG. 2), the same high speed pattern memory ("HSPM") system supports both the stimulus logic and compare logic. The input stimulus and expected output are described by test patterns which are stored in the large, high speed memories. The maximum functional test rate of the ATE is limited by the frequency with which the test patterns can be executed from memory. Prior art systems require that the entire pattern memory system be capable of supporting the highest frequency of operation of the functional test subsystem. High frequency operations, which are becoming more common with advances in technology, require larger, faster, and more complex test pattern memory subsystems to perform the functional tests.
Background: Sampling Tester
By using a prior art sampling technique, the cost and complexity of the pattern memory system and associated compare circuitry can be substantially reduced.
To cope with high-speed integrated circuits, sampling digital testers have been developed in recent years. Such testers achieve high effective sampling rates by not sampling during every clock cycle, but at fractions of the signal frequency.
The main disadvantage of using conventional sampling techniques is that multiple pattern execution iterations must be performed which increase the test time. However, test pattern execution time is typically a very small percentage of overall test time (for non-memory devices) particularly if the patterns are executed at high frequency. Therefore, the added test time is insignificant.
Some prior art systems utilized a restricted form of sampling supporting a "pin mux" mode of operation. In this mode, pairs of tester stimulus channels are combined to create two device-under-test ("DUT") cycles within one normal tester cycle. This reduces the effective number of tester channels to 1/2 the normal number of channels. In order to support the 2.times. test frequency for DUT output comparisons, a two-pass sample can be used (if the ATE does not support automatic combining of compare channels). This method only reduces the pattern memory frequency requirements by 50%, but more significantly cuts the number of available tester channels in half. With increasing test speed requirements and increasing DUT pin counts this approach is very restrictive. A sampling-type tester can reduce the pattern memory frequency requirements much more significantly without sacrificing pin count.
Background: Pattern Memory Bits
ATE systems vary in the number of pattern memory bits used to describe each pattern state for each DUT pin. The basic states typically include, but are not limited to, the following: drive_hi (data bit=1), drive_lo (data bit=0), drive_off expect_hi, expect_lo, and mask. These states are typically encoded taking advantage of mutual exclusivity and/or redundancy. Regardless of the architecture or implementation of pattern controlled pin states, the only states required to operate at full speed in a sampling-type tester are drive_hi and drive_low. Since drive_off is only required to properly load a DUT I/O pin during an output state, it too only needs to occur as frequently as the DUT outputs are being sampled. Therefore, typically only 1/3 of the total pattern information needs to be available at fill speed in a sampling-type tester.
Innovative Sampling Test System
The present application discloses a more cost effective method for ATE testing of integrated circuit chips by using sampling methods that reduce the cost and complexity of pattern memory systems. This method reduces the costs for high speed memory and its associated memory support systems by incorporating a low speed pattern memory ("LSPM") system into the ATE process.
While HSPM is still required for input to a DUT, numerous advantages are obtained with the innovative architecture.
1. Output data is sampled at a slower speed and thus requires a lower cost low-speed memory system. In the case where six common test states are used, at least two states are required at high speed whereas any of the remaining four can be sampled at slow speed. In this case, 1/3 of the total pattern memory is required to run "at speed" while the remaining 2/3 of the pattern memory can run at 1/8th the speed (in a 1:8 sampling ratio). Depending on the particular architecture, anywhere from 1/2 to 2/3 of the pattern memory system can be implemented with slower, more cost effective, pattern memory. Furthermore, the complexity of the compare and interface logic is reduced due to the reduced speed requirements for the slow pattern memory. Comparisons between DUT output data and expected data occurs at 1/nth the stimulus frequency (where n=the ratio between the stimulus frequency and the compare sample frequency). Therefore, since the sampling data must change for each of the 8 iterations, 8 different compare patterns can be executed in conjunction with the same stimulus. Since there is an 8:1 frequency ratio, each of the 8 compare patterns are 1/8th the length of the stimulus pattern so the total pattern storage requirements are the same as a conventional tester. PA0 2. Another advantage of the disclosed method includes reduced costs for memory and memory support systems related to ATE of integrated circuit chips. The cost of high frequency, high pin count ATE can be reduced by 25% to 75% using this approach. PA0 3. Another advantage of the disclosed method is it permits upgrading of older testers, since the memory systems are modular and new designs can simply be swapped into the existing system.